1. Field of the Invention
The present invention relates to an active area structure of a memory cell array.
2. Description of the Related Art
In recent years, many electronic devices which use NAND type flash memories have been commercially available. On the other hand, a large memory capacity of the NAND type flash memories is required due to multi-functions of the electronic devices, and thus the compatibility between shrink of memory cells and improvement in reliability becomes a problem (for example, see Jpn. Pat. Appln. KOKAI Publication Nos. 2002-184875, 5-88375 and 8-55920).
For example, a memory cell array of the NAND type flash memories has a periodical structure in which active areas and element isolation areas are arranged alternately with a constant spacing (for example, feature size). Further, when such a periodical structure is formed by using a conventional lithography technique, after an exposure margin (pattern blur) is taken into consideration, at least an active area at the endmost portion of the memory cell array is set as a dummy area and the width of the dummy area is made to be wider than the constant width.
A dummy cell which does not function as the memory cell but has a similar structure to that of the memory cell, is formed in the dummy area. In this case, when a writing potential is applied to a word line shared by the dummy cell and the memory cell, an electric field applied to an inter-electrode insulating film (or block insulating film) of the dummy cell becomes higher than an electric field applied to an inter-electrode insulating film (or block insulating film) of the memory cell.
The inter-electrode insulating film (or block insulating film) of the dummy cell is, therefore, easily broken by the writing potential, and this happens, the memory cell which shares the word line with the broken dummy cell will not function.
Such a problem arises not only in NAND type flash memories but also in other semiconductor memories where a large memory capacity is required.